BLOCKCNT_SDMASA=Val_0x00000000
SDMA System Address Register
| BLOCKCNT_SDMASA | 32-bit Block Count-SDMA System Address. SDMMC_HOST_CTRL2_R[HOST_VER4_ENABLE] = 0x0: The BLOCKCNT_SDMASA bit field contains the system memory address for an SDMA transfer in the 32-bit addressing Mode. When the Host Controller stops an SDMA transfer, this bit field points to the system address of the next contiguous data position. It can be accessed only if no transaction is executing. Reading this bit field during data transfers may return invalid value. 32-bit Block Count SDMMC_HOST_CTRL2_R[HOST_VER4_ENABLE] = 0x1: From the Host Controller Version 4.10 Specification, the BLOCKCNT_SDMASA bit field is redefined as 32-bit Block Count. The Host Controller decrements the block count of this bit field for every block transfer and the data transfer stops when the count reaches zero. This bit field must be accessed when no transaction is executing. Reading this bit field during data transfers may return invalid value. Note: For the SDMMC_HOST_CTRL2_R[HOST_VER4_ENABLE] = 0x0, the Host Driver does not program the system address in this bit field while operating in ADMA mode. The system address must be programmed in the ADMA System Address register (SDMMC_ADMA_SA_LOW_R). For the SDMMC_HOST_CTRL2_R[HOST_VER4_ENABLE] = 0x0, the Host Driver programs a non-zero 32-bit block count value in this bit field when Auto CMD23 is enabled for non-DMA and ADMA modes. Auto CMD23 cannot be used with SDMA. This bit field must be programmed with a non-zero value for data transfer if the 32-bit Block Count register is used instead of the 16-bit Block Count register (SDMMC_BLOCKCOUNT_R). 4294967295 (Val_0xFFFFFFFF): 4GB-1 Block 0 (Val_0x00000000): Stop count 1 (Val_0x00000001): 1 Block 2 (Val_0x00000002): 2 Blocks |